Before completing manufacturing, a display panel is subject to visual testing (VT) aimed to determine whether the display panel is working properly.
FIG. 1 is a structural diagram of a display panel in the related art. Referring to FIG. 1, the display panel includes a display area 100 provided with a plurality of data signal lines 101, and a non-display area 200 provided with a plurality of display pads 400. Each of the display pads 400 is connected to the respective data signal line 101 (specific connections are not illustrated). The display panel further includes a VT circuit 300 including a plurality of thin film transistors 301, a DO signal line, a DE signal line and an SW signal line. The odd-numbered data signal lines 101 are connected to the DO signal line through the thin film transistors 301. The even-numbered data signal lines 101 are connected to the DE signal line through the thin film transistors 301. Gate electrodes of the thin film transistors 301 are connected to the SW signal line. When the display panel is subject to the visual testing, through test pads 302, a control signal is supplied to the SW signal line and display signals are supplied to the DO signal line and the DE signal line. The SW signal line enables the thin film transistor 301 to turn on. The odd-numbered data signal lines 101 are charged through the DO signal line. The even-numbered data signal lines 101 are charged through the DE signal line. VT is performed thereof.
The VT circuit is complex and occupies much space in the non-display area 200, so it is difficult to manufacture a narrow lower non-display border for the display panel. Due to restricted space in the lower border area of the display panel, components in the VT circuit are made in small sizes and the data signal lines by the supplied display signals lead to insufficient VT charging capacity, resulting in c color mixing during display. Thus quality of the display panel cannot be tested effectively. Moreover, as a large number of components are connected to the DO signal line and the DE signal line, ESD (Electro-Static Discharge) shocks and damages tend to occur in the manufacturing process.